Non-volatile floating gate MOS memories are well known in the industry. In such devices, the conductive state of the transistor memory cell is determined by the voltage of the associated floating gate. Typically, a negatively charged floating gate is representative of a binary one state, while an uncharged floating gate is representative of a binary zero state.
More particularly, a conventional electrically programmable read only memory (EPROM) utilizes a floating (unconnected) conductive gate, in a field effect transistor structure positioned over but insulated from a channel region in a semiconductor substrate disposed between source and drain regions. A control gate (or program gate) is then provided over the floating gate (FG), but also insulated therefrom. The threshold voltage (V.sub.T) characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned "on" to permit conduction between its source (recall gate) and drain (diffusion) regions is controlled by the level of charge on-the floating gate (FG). A transistor is traditionally programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate.
The memory cell transistor's state is read by placing an operating voltage across it's source and drain and on it's control gate, and then detecting the level of current flow in between the source and drain as to whether the device is programmed to be "on" or "off" at the control gate voltage selected. A specific, single cell in a two-dimensional array of EPROM cells is addressed for reading by application of a source--drain voltage to the source and drain lines in a column containing the cell being addressed, and the application of a control gate voltage to the control gates in a row containing the cell being addressed.
In addition to the floating and control gates, an erase gate is conventionally included. The erase gate passes through each memory cell transistor closely adjacent to a surface of the floating gate but insulated therefrom by a thin tunnel dielectric. Charge is then removed from the floating gate of the cell to the erase gate when appropriate voltages are applied to all of the transistor elements. An EEPROM is a read only memory device in which the stored data may be erased and new data written instead. A widely used type of EEPROM is the floating gate field effect transistor type (see U.S. Pat. No. 5,017,977 entitled "Dual EPROM Cells On Trench Walls With Virtual Ground Buried Bit Lines"). An array of EEPROM cells is commonly referred to as a "flash" EEPROM array if the entire array of cells, or a significant group of the cells, is simultaneously erasable (i.e., in a flash).
Conventionally, to write data into a memory cell, the cell must first be erased and then written. Each of these operations takes one machine cycle, e.g., 10 milliseconds, and each requires a significant external voltage supply, such as 15-20 volts. Decoder circuits are used to sustain the needed high voltages at the appropriate cells. These high voltage circuits generally do not scale down in size with the decreasing line widths now attainable with ever improving lithographic techniques. (By comparison, to read a device typically requires only three to five applied volts and read cycle time is measured in nanoseconds.) Further, the need to erase floating gates prior to writing data therein for storage obviously adversely effects the operational speed of an array of these memory cells.
The semiconductor industry generally accepts that direct-write EEPROMs will replace both UV-erase EPROMs and flash-EEPROMs to become the main stream silicon non-volatile memory of future memory cell generations beyond 0.5 .mu.m echnology, i.e., if direct-write EEPROM devices can equal flash-EEPROM devices in density while still maintaining the re-programming flexibility of EEPROMs. Scaling of direct-write EEPROM first gate oxide results in thickness approaching the tunnel oxide (10 nm) of EEPROMs which provides a more flexible and less expensive reprogramming capability than the UV erasure required by traditional EPROMs.
One goal in the fabrication of integrated circuitry is to produce a circuit having maximum circuit density. This goal extends to the fabrication of EEPROMs. Significant increases in the direct-write EEPROM memory market are anticipated over the next decade. Many industry experts believe that direct-write EEPROMs will very likely replace magnetic storage media sometime in the near future. Any device/fabrication technique improvements which produce a denser memory array with reduced power requirements and improved performance characteristics will therefore have a significant impact in the industry.